Peng Li

No problem can be solved until it is reduced to some simple form.

  1. Wenqi Zhang, Ke Tang, Hai Wu, Mengna Wang, Yongliang Shen, Guiyang Hou, Zeqi Tan, Peng Li*, Yueting Zhuang, Weiming Lu. Agent-Pro: Learning to Evolve via Policy-Level Reflection and Optimization. Accepted by ICLR 2024 Workshop on Large Language Model (LLM) Agents.
  2. Fei Gao, Dai Lingna, Jingjie Zhu, Mei Du, Zhang Yiyuan, Maoying Qiao, Chenghao Xia, Nannan Wang, Peng Li*. Human-Robot Interactive Creation of Artistic Portrait Drawings. Accepted by International Conference on Robotics and Automation (ICRA 2024).
  3. Jingjie Zhu, Lingna Dai, Chenghao Xia, Chenyang Jiang, Weiyu Weng, Yiyuan Zhang, Jinglin Zhou, Fei Gao, Peng Li, Mingrui Zhu, Nannan Wang, Artistic Portrait Applet, Robot, and Printer. CAAI International Conference on Artificial Intelligence (2022). Finalist of Best Demo Award.
  4. Wenqi Zhang, Kai Zhao, Peng Li, Xiao Zhu, Yongliang Shen, Yanna Ma, Yingfeng Chen, Weiming Lu. A Closed-Loop Perception, Decision-Making and Reasoning Mechanism for Human-Like Navigation. In Proceedings of the 31st International Joint Conference on Artificial Intelligence (IJCAI 2022), pages 4717–4724 July 23-29, 2022, Messe Wien, Vienna, Austria.
  5. Liqiang Lu, Yicheng Jin, Hangrui Bi, Zizhang Luo, Peng Li, Tao Wang, Yun Liang. Sanger: A Co-Design Framework for Enabling Sparse Attention using Reconfigurable Architecture. In Proceedings of the 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2021), pages 977-991, October 16-20, 2021, Athens, Greece.
  6. Wenqi Zhang, Kai Zhao, Peng Li*, Xiao Zhu, Faping Ye, Weijie Jiang, Huiqiao Fu, Tao Wang. Learning to Navigate in a VUCA Environment: Hierarchical Multi-expert Approach. In Proceedings of IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS’21, pages 9254-9261, 2021.
  7. Fei Gao, Jingjie Zhu, Weiyu Weng, Chenyang Jiang, Xiang Li, Xiao Zhu, Lingna Dai, Peng Li. High-quality Face Sketch Synthesis via Geometric Normalization and Regularization. Accepted by the IEEE International Conference on Multimedia and Expo (ICME) 2021, Demo Track, Best Demo Runner up Award ,ICME’21.
  8. Huiqiao Fu, Kaiqiang Tang, Peng Li, Wenqi Zhang, Xinpeng Wang, Guizhou Deng, Tao Wang, Chunlin Chen. Deep Reinforcement Learning for Multi-contact Motion Planning of Hexapod Robots. In Proceedings of the Thirtieth International Joint Conference on Artificial Intelligence (IJCAI 2021), pages 2381–2388, Virtual Event / Montreal, Canada, 19-27, August 2021.
  9. Fei Gao，Jingjie Zhu，Zeyuan Yu，Peng Li* and Tao Wang. Making Robots Draw A Vivid Portrait In Two Minutes. In Proceedings of IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS’20, pages 9585-9591, 2020.
  10. Young kyu Choi, Peng Zhang, Peng Li, and Jason Cong. Hlscope+: Fast and Accurate Performance Estimation for FPGA HLS. In Proceedings of the International Conference on Computer-Aided Design, ICCAD’17, pages 691–698, 2017.
  11. Guangyu Sun, Chao Zhang, Peng Li, Tao Wang, and Yiran Chen. Statistical Cache Bypassing for Non-Volatile Memory. IEEE Transaction on Computers, 65:3427–3440, 2016.
  12. Jason Cong, Peng Li, Bingjun Xiao, and Peng Zhang. An Optimal Microarchitecture for Stencil Computation Acceleration based on Nonuniform Partitioning of Data Reuse Buffers. IEEE Transaction on CAD of Integrated Circuits and Systems, 35:407–418, 2016.
  13. Chen Zhang, Peng Li, Guangyu Sun, Yijin Guan, Bingjun Xiao, and Jason Cong. Exploring FPGA-based Accelerator Design for Deep Convolutional Neural Networks. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA’15, Nomination for Best Paper Award , pages 161–170, 2015.
  14. Peng Li, Peng Zhang, Pouchet Louis-Noel, and Jason Cong. Resource-Aware Throughtput Optimization for High-Level Synthesis. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA’15, pages 200–209, 2015.
  15. Shuangchen Li, Ang Li, Yuan Zhe, Yongpan Liu, Peng Li, Guangyu Sun, Yu Wang, Huazhong Yang, and Yuan Xie. Leveraging Emerging Nonvolatile Memory in High-Level Synthesis with Loop Thransformations. In Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED’15, pages 61–66, 2015.
  16. Wentai Zhang, Li Shen, Thomas Page, Guojie Luo, Peng Li, Ming Jiang, Peter Maass, and Jason Cong. FPGA Acceleration by Asynchronous Parallelization for Simultaneous Image Reconstruction and Segmentation based on the Mumford-Shah Regularization. In SPIE Optical Engineering + Applications, SPIE’15, 2015.
  17. Chao Zhang, Guangyu Sun, Peng Li, Tao Wang, Dimin Niu, and Yiran Chen. A Statistics based Cache Bypassing Method for Asymmetric-access Caches. In Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED’14, pages 345–350, 2014.
  18. Jason Cong, Peng Li, Bingjun Xiao, and Peng Zhang. An Optimal Microarchitecture for Stencil Computation Acceleration based on Non-Uniform Partitioning of Data Reuse Buffers. In Proceedings of the 51th Annual Design Automation Conference, DAC’14, pages 407–418, 2014.
  19. Peng Li, Thomas Page, Guojie Luo, Wentai Zhang, Pei Wang, Peter Maass, Ming Jiang, and Jason Cong. FPGA Acceleration for Simultaneous Medical Image Reconstruction and Segmentation (Poster). In The 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM’14, 2014.
  20. Yuxin Wang, Peng Li, and Jason Cong. Theory and Algorithm for Generalized Multidimensional Memory Partitioning in High-Level Synthesis. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA’14, pages 199–208, 2014.
  21. Peng Li, Louis-Noel Pouchet, Deming Chen, and Jason Cong. Loop Transformations for Throughput Optimization in High-Level Synthesis (Poster). In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA’14, page 245, 2014.
  22. Peng Li, Louis-Noel Pouchet, and Jason Cong. Throughput Optimization for High-Level Synthesis Using Resource Constraints. In 4th International Workshop on Polyhedral Compilation Techniques, IMPACT’14, 2014.
  23. Wei Zuo, Peng Li, Deming Chen, Pouchet Louis-Noel, Shunan Zhong, and Jason Cong. Improving Polyhedral Code Generation for High-Level Synthesis. In Proceedings of the Annual International Conference on Hardware/Software Codesign and System Synthesis, CODES-ISSS ’13, Best Paper Award (1 out of 111 submissions) , pages 1–10, 2013.
  24. Yuxin Wang, Peng Li, Peng Zhang, Chen Zhang, and Jason Cong. Memory Partitioning for Multidimensional Arrays in High-Level Synthesis. In Proceedings of the 50th Annual Design Automation Conference, DAC ’13, pages 12:1–12:8, 2013.
  25. Cong Yan, Peng Li, and Guojie Luo. Customized Physical Design for Partitioned On-Chip Memory Module in FPGA (work-in-progress workshop. In 50th Annual Design Automation Conference, DAC ’13.
  26. Peng Li, Angshuman Parashar, Michael Pellauer, Tao Wang, and Joel Emer. A Hierarchical Architectural Framework for Reconfigurable Logic Computing. In Proceedings of the 27th IEEE Parallel and Distributed Processing Symposium Workshops & PhD Forum, IPDPSW’13, pages 287–292, 2013.
  27. Wei Zuo, Yun Liang, Peng Li, Kyle Rupnow, Deming Chen, and Jason Cong. Improving High Level Synthesis Optimization Opportunity through Polyhedral Transformations. In Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, FPGA ’13, pages 9–18, New York, NY, USA, 2013. ACM.
  28. Yuxin Wang, Peng Li, Chen Zhang, and Jason Cong. Automatic Multidimensional Memory Partitioning for FPGA-based Accelerators (poster). In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA’13, 2013.
  29. Peng Li, Yuxin Wang, Peng Zhang, Guojie Luo, Tao Wang, and Jason Cong. Memory Partitioning and Scheduling Co-Optimization in Behavioral Synthesis. In Proceedings of the International Conference on Computer-Aided Design, ICCAD ’12, pages 488–495, New York, NY, USA, 2012. ACM.
  30. Tao Wang, Zhihong Yu, Peng Li, Yuan Liu, Dong Liu, and Joel Emer. An Architecture and Mechanism for Supporting Speculative Execution of a Context-full Reconfigurable Function Unit. In Workshop on the Intersections of Computer Architecture and Reconfigurable Logic, CARL’10, 2010.
  31. Sadagopan Srinivasan, Li Zhao, Lin Sun, Zhen Fang, Peng Li, Tao Wang, Ravishankar Iyer, and Dong Liu. Performance Characterization and Acceleration of Optical Character Recognition on Handheld Platforms. In Proceedings of the IEEE International Symposium on Workload Characterization, IISWC ’10, pages 1–10, 2010.
  32. Ming Cong, Hong An, Lu Cao, Yuan Liu, Peng Li, Tao Wang, Zhihong Yu, and Dong Liu. Pattern-unit based Regular Expression Matching with Reconfigurable Function Unit. In Proceedings of the International Conference on Computational Science and its Applications, ICCSA’10, pages 427–440, 2010.
  33. Tao Wang, Peng Li, Yuan Liu, Zhiyuan Zhang, Angshuman Parashar, Azam Barkatullah, Dong Liu, and Joel Emer. Using Reconfigurable Logic to Replace Fixed-function Blocks in SoCs. In Workshop on SoC Architecture, Accelerators and Workloads, SAW’10, 2010.
  34. Yanteng Sun, Peng Li, Guochang Gu, Yuan Wen, Yuan Liu, and Dong Liu. Accelerating HMM Search on FPGAs Using Systolic Array based Architecture. In IEEE International Workshop on High Performance Computational Biology, HiComb’09, pages 1–8, 2009.
  35. Yanteng Sun, Peng Li, Guochang Gu, Yuan Wen, Yuan Liu, and Dong Liu. HMMer Acceleration Using Systolic Array based Reconfigurable Architecture (Poster). In Proceedings of the ACM/SIGDA International Symposium of Field Programmable Gate Arrays, FPGA’09, page 282, 2009.
  36. Peng Li, Dongsheng Wang, Haixia Wang, Meijuan Lu, Chongmin Li, and Weimin Zheng. Software Support for LIRAC Architecture. Tsinghua Science and Technology, 6:700–706, 2007.
  37. Haixia Wang, Dongsheng Wang, Peng Li, Jinglei Wang, and Chongmin Li. Reducing Network Traffic of Token Protocol Using Sharing Relation Cache. Tsinghua Science and Technology, 6:691–699, 2007.
  38. Haixia Wang, Dongsheng Wang, Peng Li, Jinglei Wang, and Xianping Fu. Exploit Temporal Locality of Shared Data in SRC-enabled CMP. In Proceedings of the International Conference on Network and Parallel Computing, NPC’07, pages 384–393, 2007.
  39. Peng Li, Dongsheng Wang, Haixia Wang, Meijuan Lu, and Weimin Zheng. LIRAC: Using Live Range Information to Optimize Memory Access. In Proceedings of the International Conference on Architecture of Computing Systems, ARCS ’07, pages 28–42, 2007.
  40. Haixia Wang, Dongsheng Wang, and Peng Li. SRC-based Cache Coherence Protocol in Chip Multiprocessor. In Japan-China Joint Workshop on Frontier of Computer Science and Technology, FCST’06, pages 60–70, 2006.
  41. Peng Li, Dongsheng Wang, Songliu Guo, Tao Tian, and Weimin Zheng. Live Range Aware Cache Architecture. In Proceedings of the Asia-Pacific Computer Systems Architecture Conference, ACSAC ’06, pages 409–415, 2006.
  42. Dongsheng Wang Haixia Wang and Peng Li. Acceleration Techniques for Chip-Multiprocessor Simulator Debug. In Proceedings of the Asia-Pacific Computer Systems Architecture Conference, ACSAC ’06, pages 509–515, 2006.
  43. Youhui Zhang, Peng Li, Dongsheng Wang, and Weimin Zheng. Seamless Peripherals Integration for Network Computers based on the Reversed Server Message Block Protocol. In Proceedings of the International Conference on Networking and Services, ICNS’06, pages 112:1–112:6, 2006